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Modeling and Test Generation Algorithms for MOS Circuits
May 1985 (vol. 34 no. 5)
pp. 426-433
S.K. Jain, AT& T Bell Laboratories
An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.
Index Terms:
transistor faults, D-algorithm, integrated circuit testing, MOS circuits, test generation
Citation:
S.K. Jain, V.D. Agrawal, "Modeling and Test Generation Algorithms for MOS Circuits," IEEE Transactions on Computers, vol. 34, no. 5, pp. 426-433, May 1985, doi:10.1109/TC.1985.1676582
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