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Issue No.05 - May (1985 vol.34)
pp: 404-411
L.M. Ni , Department of Computer Science, Michigan State University
ABSTRACT
Vector-reduction arithmetic accepts vectors as inputs and produces scalars as outputs. This class of vector operation forms the basis of many scientific computations, such as inner product and finding the maximum among the vector components. Vector reduction on a pipeline processor demands a feedback connection around the pipeline. Since the output of such a pipeline depends on the previous output, improper control of the feedback input may destroy the benefit from pipelining. Two new vector-reduction techniques are proposed in this paper. In addition to saving reduction time and eliminating intermediate storage (as compared to Kuck's method and Kogge's method), the new methods will greatly simplify the machine-level programming effort needed to implement vector-reduction operations. An interleaved technique is introduced to reduce multiple vectors to corresponding scalars using the same arithmetic pipeline. The pipeline can be fully utilized by interleaving multiple vector-reduction processes. The proposed techniques can be applied to improve the performance of vector-arithmetic pipelines in scientific supercomputers.
INDEX TERMS
VLSI architecture, Arithmetic pipelines, interleaving, matrix algebra, multiple vector processing, vector reduction
CITATION
L.M. Ni, null Kai Hwang, "Vector-Reduction Techniques for Arithmetic Pipelines", IEEE Transactions on Computers, vol.34, no. 5, pp. 404-411, May 1985, doi:10.1109/TC.1985.1676580
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