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A VLSI Design of a Pipeline Reed-Solomon Decoder
May 1985 (vol. 34 no. 5)
pp. 393-403
H.M. Shao, Communication System Research Section, Jet Propulsion Laboratory, California Institute of Technology
A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code.
Index Terms:
VLSI, Pipeline, Reed-Solomon decoder, systolic array
Citation:
H.M. Shao, T.K. Truong, L.J. Deutsch, J.H. Yuen, I.S. Reed, "A VLSI Design of a Pipeline Reed-Solomon Decoder," IEEE Transactions on Computers, vol. 34, no. 5, pp. 393-403, May 1985, doi:10.1109/TC.1985.1676579
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