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An Analysis of Processor-Memory Interconnection Networks
March 1985 (vol. 34 no. 3)
pp. 279-283
| ASCII Text | x | ||
| L.N. Bhuyan, "An Analysis of Processor-Memory Interconnection Networks," IEEE Transactions on Computers, vol. 34, no. 3, pp. 279-283, March, 1985. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1985.1676571, author = {L.N. Bhuyan}, title = {An Analysis of Processor-Memory Interconnection Networks}, journal ={IEEE Transactions on Computers}, volume = {34}, number = {3}, issn = {0018-9340}, year = {1985}, pages = {279-283}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1985.1676571}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Analysis of Processor-Memory Interconnection Networks IS - 3 SN - 0018-9340 SP279 EP283 EPD - 279-283 A1 - L.N. Bhuyan, PY - 1985 KW - multiprocessor performance KW - Bandwidth KW - crossbar switches KW - favorite memories KW - multistage interconnection networks VL - 34 JA - IEEE Transactions on Computers ER - | |||
An interference analysis of the interconnection networks (IN's) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module is equally likely to be addressed by a processor and when a processor has a favorite memory. It is shown that for a higher rate of favorite requests, the delta networks perform close to a crossbar.
Index Terms:
multiprocessor performance, Bandwidth, crossbar switches, favorite memories, multistage interconnection networks
Citation:
L.N. Bhuyan, "An Analysis of Processor-Memory Interconnection Networks," IEEE Transactions on Computers, vol. 34, no. 3, pp. 279-283, March 1985, doi:10.1109/TC.1985.1676571
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