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An Analysis of Processor-Memory Interconnection Networks
March 1985 (vol. 34 no. 3)
pp. 279-283
L.N. Bhuyan, Department of Electrical and Computer Engineering, University of Southwestern Louisiana
An interference analysis of the interconnection networks (IN's) for tightly coupled multiprocessors is presented in this correspondence. The interconnections considered are crossbars and delta networks. Two situations are examined: when a memory module is equally likely to be addressed by a processor and when a processor has a favorite memory. It is shown that for a higher rate of favorite requests, the delta networks perform close to a crossbar.
Index Terms:
multiprocessor performance, Bandwidth, crossbar switches, favorite memories, multistage interconnection networks
Citation:
L.N. Bhuyan, "An Analysis of Processor-Memory Interconnection Networks," IEEE Transactions on Computers, vol. 34, no. 3, pp. 279-283, March 1985, doi:10.1109/TC.1985.1676571
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