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Address Generation in an Array Processor
February 1985 (vol. 34 no. 2)
pp. 170-173
| ASCII Text | x | ||
| E.O. Nwachukwu, "Address Generation in an Array Processor," IEEE Transactions on Computers, vol. 34, no. 2, pp. 170-173, February, 1985. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1985.1676554, author = {E.O. Nwachukwu}, title = {Address Generation in an Array Processor}, journal ={IEEE Transactions on Computers}, volume = {34}, number = {2}, issn = {0018-9340}, year = {1985}, pages = {170-173}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1985.1676554}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Address Generation in an Array Processor IS - 2 SN - 0018-9340 SP170 EP173 EPD - 170-173 A1 - E.O. Nwachukwu, PY - 1985 KW - real-value FFT KW - Address indexing unit KW - array processing and manipulation KW - counter/multiplexer principle VL - 34 JA - IEEE Transactions on Computers ER - | |||
This correspondence describes the implementation of a versatile hardware address indexing unit (AIU) capable of generating a multiplicity of address sequences for both array processing and array manipulation. The AIU utilizes a counter/multiplexer principle and incorporates an address logic for implementing real-value FFT based on a standard complex form.
Index Terms:
real-value FFT, Address indexing unit, array processing and manipulation, counter/multiplexer principle
Citation:
E.O. Nwachukwu, "Address Generation in an Array Processor," IEEE Transactions on Computers, vol. 34, no. 2, pp. 170-173, Feb. 1985, doi:10.1109/TC.1985.1676554
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