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Issue No.02 - February (1985 vol.34)
pp: 170-173
E.O. Nwachukwu , Department of Computer Science, University of Port Harcourt
ABSTRACT
This correspondence describes the implementation of a versatile hardware address indexing unit (AIU) capable of generating a multiplicity of address sequences for both array processing and array manipulation. The AIU utilizes a counter/multiplexer principle and incorporates an address logic for implementing real-value FFT based on a standard complex form.
INDEX TERMS
real-value FFT, Address indexing unit, array processing and manipulation, counter/multiplexer principle
CITATION
E.O. Nwachukwu, "Address Generation in an Array Processor", IEEE Transactions on Computers, vol.34, no. 2, pp. 170-173, February 1985, doi:10.1109/TC.1985.1676554
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