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Fault-Tolerant Multiprocessor Link and Bus Network Architectures
January 1985 (vol. 34 no. 1)
pp. 33-45
D.K. Pradhan, Department of Electrical and Computer Engineering, University of Massachusetts
This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.
Index Terms:
shuffle-exchange graph, Algorithmic routing, circuit switching, connectivity, diameter of graphs, fault-tolerant communication network, multiple bus network, multiprocessor networks, packet switching, regular graphs, regular networks, shared-bus fault tolerance
Citation:
D.K. Pradhan, "Fault-Tolerant Multiprocessor Link and Bus Network Architectures," IEEE Transactions on Computers, vol. 34, no. 1, pp. 33-45, Jan. 1985, doi:10.1109/TC.1985.1676513
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