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Issue No.12 - December (1984 vol.33)
pp: 1221-1246
J.L. Hennessy , Computer Systems Laboratory, Stanford University
ABSTRACT
A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler. In VLSI, the issue of implementation of an instruction set architecture is significant in determining the features of the architecture. Recent processor architectures have focused on two major trends: large microcoded instruction sets and simplified, or reduced, instruction sets. The attractiveness of these two approaches is affected by the choice of a single-chip implementation. The two different styles require different tradeoffs to attain an implementation in silicon with a reasonable area. The two styles consume the chip area for different purposes, thus achieving performance by different strategies. In a VLSI implementation of an architecture, many problems can arise from the base technology and its limitations. Although circuit design techniques can help alleviate many of these problems, the architects must be aware of these limitations and understand their implications at the instruction set level.
INDEX TERMS
VLSI, Computer organization, instruction issue, instruction set design, memory mapping, microprocessors, pipelining, processor architecture, processor implementation
CITATION
J.L. Hennessy, "VLSI Processor Architecture", IEEE Transactions on Computers, vol.33, no. 12, pp. 1221-1246, December 1984, doi:10.1109/TC.1984.1676395
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