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An Efficient Implementation of Search Trees on [lg N + 1] Processors
November 1984 (vol. 33 no. 11)
pp. 1038-1041
M.J. Carey, Department of Computer Science, University of Wisconsin
A scheme for maintaining a balanced search tree on ?lg N + 1?parallel processors is described. The scheme is almost fully pipelined: ?lg N + 1?/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the total delay per tree operation is O(lg N), and one tree operation completes every 0(1) time units.
Index Terms:
special-purpose architectures, Algorithms for VLSI, dictionary search, pipelining, search trees
Citation:
M.J. Carey, C.D. Thompson, "An Efficient Implementation of Search Trees on [lg N + 1] Processors," IEEE Transactions on Computers, vol. 33, no. 11, pp. 1038-1041, Nov. 1984, doi:10.1109/TC.1984.1676379
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