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An Efficient Implementation of Search Trees on [lg N + 1] Processors
November 1984 (vol. 33 no. 11)
pp. 1038-1041
| ASCII Text | x | ||
| M.J. Carey, C.D. Thompson, "An Efficient Implementation of Search Trees on [lg N + 1] Processors," IEEE Transactions on Computers, vol. 33, no. 11, pp. 1038-1041, November, 1984. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1984.1676379, author = {M.J. Carey and C.D. Thompson}, title = {An Efficient Implementation of Search Trees on [lg N + 1] Processors}, journal ={IEEE Transactions on Computers}, volume = {33}, number = {11}, issn = {0018-9340}, year = {1984}, pages = {1038-1041}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1984.1676379}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Efficient Implementation of Search Trees on [lg N + 1] Processors IS - 11 SN - 0018-9340 SP1038 EP1041 EPD - 1038-1041 A1 - M.J. Carey, A1 - C.D. Thompson, PY - 1984 KW - special-purpose architectures KW - Algorithms for VLSI KW - dictionary search KW - pipelining KW - search trees VL - 33 JA - IEEE Transactions on Computers ER - | |||
A scheme for maintaining a balanced search tree on ?lg N + 1?parallel processors is described. The scheme is almost fully pipelined: ?lg N + 1?/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the total delay per tree operation is O(lg N), and one tree operation completes every 0(1) time units.
Index Terms:
special-purpose architectures, Algorithms for VLSI, dictionary search, pipelining, search trees
Citation:
M.J. Carey, C.D. Thompson, "An Efficient Implementation of Search Trees on [lg N + 1] Processors," IEEE Transactions on Computers, vol. 33, no. 11, pp. 1038-1041, Nov. 1984, doi:10.1109/TC.1984.1676379
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