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Instruction Issue Logic in Pipelined Supercomputers
November 1984 (vol. 33 no. 11)
pp. 1013-1022
S. Weiss, Department of Computer Sciences, University of Wis-consin
Basic principles and design tradeoffs for control of pipelined processors are first discussed. We concentrate on register-register architectures like the CRAY-1 where pipeline control logic is localized to one or two pipeline stages and is referred to as "instruction issue logic." Design tradeoffs are explored by giving designs for a variety of instruction issue methods that represent a range of complexity and sophistication. These vary from the CRAY-1 issue logic to a version of Tomasulo's algorithm, first used in the IBM 360/91 floating point unit. Also studied are Thornton's "scoreboard" algorithm used on the CDC 6600 and an algorithm we have devised. To provide a standard for comparison, all the issue methods are used to implement the CRAY-1 scalar architecture. Then, using a simulation model and the Lawrence Livermore Loops compiled with the CRAY Fortran compiler, performance results for the various issue methods are given and discussed.
Index Terms:
Tomasulo's algorithm, CDC 6600 scoreboard, control logic, CRAY-1, IBM 360/91, instruction issue logic, performance simujation, pipelined computers, supercomputers
Citation:
S. Weiss, J.E. Smith, "Instruction Issue Logic in Pipelined Supercomputers," IEEE Transactions on Computers, vol. 33, no. 11, pp. 1013-1022, Nov. 1984, doi:10.1109/TC.1984.1676375
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