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Measuring the Parallelism Available for Very Long Instruction Word Architectures
November 1984 (vol. 33 no. 11)
pp. 968-976
A. Nicolau, Department of Computer Science, Cornell University
Long instruction word architectures, such as attached scientific processors and horizontally microcoded CPU's, are a popular means of obtaining code speedup via fine-grained parallelism. The falling cost of hardware holds out the hope of using these architectures for much more parallelism. But this hope has been diminished by experiments measuring how much parallelism is available in the code to start with. These experiments implied that even if we had infinite hardware, long instruction word architectures could not provide a speedup of more than a factor of 2 or 3 on real programs.
Index Terms:
VLIW (very long instruction word) architectures, Memory antialiasing, microcode, multiprocessors, parallelism, trace scheduling
Citation:
A. Nicolau, J.A. Fisher, "Measuring the Parallelism Available for Very Long Instruction Word Architectures," IEEE Transactions on Computers, vol. 33, no. 11, pp. 968-976, Nov. 1984, doi:10.1109/TC.1984.1676371
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