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I.V. Ramakrishnan, P.J. Varman, "Modular Matrix Multiplication on a Linear Array," IEEE Transactions on Computers, vol. 33, no. 11, pp. 952958, November, 1984.  
BibTex  x  
@article{ 10.1109/TC.1984.1676369, author = {I.V. Ramakrishnan and P.J. Varman}, title = {Modular Matrix Multiplication on a Linear Array}, journal ={IEEE Transactions on Computers}, volume = {33}, number = {11}, issn = {00189340}, year = {1984}, pages = {952958}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1984.1676369}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Modular Matrix Multiplication on a Linear Array IS  11 SN  00189340 SP952 EP958 EPD  952958 A1  I.V. Ramakrishnan, A1  P.J. Varman, PY  1984 KW  VLSI KW  Array processors KW  linear array KW  matrix multiplication KW  modular KW  parallel processing VL  33 JA  IEEE Transactions on Computers ER   
A matrix multiplication algorithm on a linear array of processing elements is described. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading smaller arrays. Each of the matrix elements is read only once from a fixed I/O port and the algorithm does not use global broadcasting. It is also shown that the proposed algorithm computes the n3 scalar products (where n is the size of the two matrices being multiplied) using an optimal number of processing elements.
Index Terms:
VLSI, Array processors, linear array, matrix multiplication, modular, parallel processing
Citation:
I.V. Ramakrishnan, P.J. Varman, "Modular Matrix Multiplication on a Linear Array," IEEE Transactions on Computers, vol. 33, no. 11, pp. 952958, Nov. 1984, doi:10.1109/TC.1984.1676369
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