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Modular Matrix Multiplication on a Linear Array
November 1984 (vol. 33 no. 11)
pp. 952-958
I.V. Ramakrishnan, Department of Computer Science, University of Maryland
A matrix multiplication algorithm on a linear array of processing elements is described. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by cascading smaller arrays. Each of the matrix elements is read only once from a fixed I/O port and the algorithm does not use global broadcasting. It is also shown that the proposed algorithm computes the n3 scalar products (where n is the size of the two matrices being multiplied) using an optimal number of processing elements.
Index Terms:
VLSI, Array processors, linear array, matrix multiplication, modular, parallel processing
Citation:
I.V. Ramakrishnan, P.J. Varman, "Modular Matrix Multiplication on a Linear Array," IEEE Transactions on Computers, vol. 33, no. 11, pp. 952-958, Nov. 1984, doi:10.1109/TC.1984.1676369
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