The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.10 - October (1984 vol.33)
pp: 923-927
B.R. Iyer , IBM T. J. Watson Research Center
ABSTRACT
In this correspondence we consider a model for dynamic memories that are characterized by small cell fan-out and a small number of I/O ports. Many schemes have been proposed in the literature to interconnect dynamic memory cells. These usually exhibit a tradeoff between random and block access times. We propose a scheme that combines the interconnection scheme of a previous work with the idea of interleaving. With this we show that both random and block access times can be optimized. We analyze access times for our scheme and compare them to those for other schemes in the literature. We define delay between two block accesses and compare the dynamic memory organization schemes on the basis of delay.
INDEX TERMS
interconnection networks, Access algorithm, access times, dynamic memories
CITATION
B.R. Iyer, "Dynamic Memory Interconnections for Rapid Access", IEEE Transactions on Computers, vol.33, no. 10, pp. 923-927, October 1984, doi:10.1109/TC.1984.1676354
5 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool