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A Robust Matrix-Multiplication Array
October 1984 (vol. 33 no. 10)
pp. 919-922
P.J. Varman, Department of Electrical and Computer Engineering, Rice University
Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host computer as a peripheral and the I/O bandwidth required to drive the array is a constant, independent of the problem size. Multiplication of two n x n matrices requires O(n) processors and has a time complexity of O(n2) cydes.
Index Terms:
wafer-scale integration, Array processor, matrix multiplication, reconfigurability, robust, VLSI
Citation:
P.J. Varman, I.V. Ramakrishnan, D.S. Fussell, "A Robust Matrix-Multiplication Array," IEEE Transactions on Computers, vol. 33, no. 10, pp. 919-922, Oct. 1984, doi:10.1109/TC.1984.1676353
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