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Issue No.10 - October (1984 vol.33)
pp: 906-911
null In-Shek Hsu , Department of Electrical Engineering, University of Southern California
ABSTRACT
Berlekamp has developed for the California Institute of Technology Jet Propulsion Laboratory (JPL) a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes, using a dual basis over a Galois field. The conventional RS encoder for long codes often requires lookup tables to perform multiplication of two field elements. Berlekamp's algorithm requires only shifting and EXCLUSIVE OR operations. It is shown in this paper that the new dual-basis (255,223) RS encoder can be realized readily on a single VLSI chip with NMOS technology.
INDEX TERMS
VLSI, Berlekamp's bit-serial multiplier, dual basis, Reed-Solomon code, trace
CITATION
null In-Shek Hsu, I.S. Reed, T.K. Truong, null Ke Wang, null Chiunn-Shyong Yeh, L.J. Deutsch, "The VLSI Implementation of a Reed?Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm", IEEE Transactions on Computers, vol.33, no. 10, pp. 906-911, October 1984, doi:10.1109/TC.1984.1676351
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