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Input Variable Assignment and Output Phase Optimization of PLA's
October 1984 (vol. 33 no. 10)
pp. 879-894
T. Sasao, Department of Electronic Engineering, Osaka University
A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA's and PLA's with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants.
Index Terms:
switching theory, Adder, complexity of logic circuits, decoder assignment, essential prime implicants, logic design, output phase optimization, programmable logic array
Citation:
T. Sasao, "Input Variable Assignment and Output Phase Optimization of PLA's," IEEE Transactions on Computers, vol. 33, no. 10, pp. 879-894, Oct. 1984, doi:10.1109/TC.1984.1676349
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