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Computational Geometry on a Systolic Chip
September 1984 (vol. 33 no. 9)
pp. 774-785
B. Chazelle, Department of Computer Science, Brown University
This paper describes systolic algorithms for a number of geometric problems. For the sake of realism we restrict our investigation to one-dimensional arrays whose communication links with the outside are located at the end cells. Implementations yielding maximal throughput are given for solving dynamic versions of convex hull, inclusion, range and intersection search, planar point location, intersection, triangulation, and closest-point problems.
Index Terms:
VLSI, Analysis of algorithms, computational geometry, convolution, parallel computation, pipelining, real-time algorithms, systolic arrays
Citation:
B. Chazelle, "Computational Geometry on a Systolic Chip," IEEE Transactions on Computers, vol. 33, no. 9, pp. 774-785, Sept. 1984, doi:10.1109/TC.1984.1676494
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