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Signature Testing of Sequential Machines
August 1984 (vol. 33 no. 8)
pp. 762-764
Syed Zahoor Hassan, Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305.
A new approach to the testing of sequential machines is presented which employs signature analysis. In the conventional scheme of testing sequential finite state machines, distinguishing and transfer sequences are used. For the purposes of testing sequential machines by signature analysis, a signature distinguishing sequence is defined. An algorithm for augmenting a sequential machine by introducing an extra input is presented. This yields a sequential machine that has a signature distinguishing sequence. The additional cost in terms of the chip area for a programmable logic array (PLA) implementation is calculated.
Citation:
Syed Zahoor Hassan, "Signature Testing of Sequential Machines," IEEE Transactions on Computers, vol. 33, no. 8, pp. 762-764, Aug. 1984, doi:10.1109/TC.1984.5009368
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