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Issue No.08 - August (1984 vol.33)
pp: 737-739
Shigeo Kaneda , First Research Section, Communication Principles Research Division, Musashino Electrical Communication Laboratory, N. T. T., Midori-cho, Musashino-shi, Tokyo, Japan.
ABSTRACT
Error correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2<sup>r-1</sup> - 2<sup>[r/2]</sup>, where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes.
CITATION
Shigeo Kaneda, "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications", IEEE Transactions on Computers, vol.33, no. 8, pp. 737-739, August 1984, doi:10.1109/TC.1984.5009359
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