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Fault Tolerance in Binary Tree Architectures
June 1984 (vol. 33 no. 6)
pp. 568-572
C.S. Raghavendra, Department of Electrical Engineering-Systems, University of Southern California
Binary tree network architectures are applicable in the design of hierarchical computing systems and in specialized high-performance computers. In this correspondence, the reliability and fault tolerance issues in binary tree architecture with spares are considered. Two different fault-tolerance mechanisms are described and studied, namely: 1) scheme with spares; and 2) scheme with performance degradation. Reliability analysis and estimation of the fault-tolerant binary tree structures are performed using the interactive ARIES 82 program. The discussion is restricted to the topological level, and certain extensions of the schemes are also discussed.
Index Terms:
spare processors, Binary tree, fault tolerance, network architecture, performance degradation, reliability modeling
Citation:
C.S. Raghavendra, A. AVIvizienis, M.D. Ercegovac, "Fault Tolerance in Binary Tree Architectures," IEEE Transactions on Computers, vol. 33, no. 6, pp. 568-572, June 1984, doi:10.1109/TC.1984.1676483
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