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The Design of Easily Testable VLSI Array Multipliers
June 1984 (vol. 33 no. 6)
pp. 554-560
J.P. Shen, SRC-CMU Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie-Mellon University
Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures is studied in detail. The conventional design of the carry?save array multiplier is modified. The modified design is shown to be C-testable and requires only 16 test patterns. Similar results are obtained for the Baugh?Wooley two's complement array multiplier. A modified design of the Baugh?Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The C-testability of two other array multipliers, namely the carry?propagate and the TRW designs, is also presented.
Index Terms:
VLSI testing, Array multipliers, C-testability, design for testability, exhaustive testing
Citation:
J.P. Shen, F.J. Ferguson, "The Design of Easily Testable VLSI Array Multipliers," IEEE Transactions on Computers, vol. 33, no. 6, pp. 554-560, June 1984, doi:10.1109/TC.1984.1676480
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