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June 1984 (vol. 33 no. 6)
pp. 493-506
| ASCII Text | x | ||
| Y. Tamir, C.H. Sequin, "Design and Application of Self-Testing Comparators Implemented with MOS PLA's," IEEE Transactions on Computers, vol. 33, no. 6, pp. 493-506, June, 1984. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1984.1676473, author = {Y. Tamir and C.H. Sequin}, title = {Design and Application of Self-Testing Comparators Implemented with MOS PLA's}, journal ={IEEE Transactions on Computers}, volume = {33}, number = {6}, issn = {0018-9340}, year = {1984}, pages = {493-506}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1984.1676473}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Design and Application of Self-Testing Comparators Implemented with MOS PLA's IS - 6 SN - 0018-9340 SP493 EP506 EPD - 493-506 A1 - Y. Tamir, A1 - C.H. Sequin, PY - 1984 KW - two-rail code checker KW - Concurrent error detection KW - duplication and matching KW - faults in VLSI circuits KW - MOS PLA fault model KW - programmable logic array KW - self-testing comparator VL - 33 JA - IEEE Transactions on Computers ER - | |||
A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.
Index Terms:
two-rail code checker, Concurrent error detection, duplication and matching, faults in VLSI circuits, MOS PLA fault model, programmable logic array, self-testing comparator
Citation:
Y. Tamir, C.H. Sequin, "Design and Application of Self-Testing Comparators Implemented with MOS PLA's," IEEE Transactions on Computers, vol. 33, no. 6, pp. 493-506, June 1984, doi:10.1109/TC.1984.1676473
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