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A Loop-Structured Switching Network
May 1984 (vol. 33 no. 5)
pp. 450-455
F.S. Wong, Department of Electrical Engineering, University of British Columbia
This paper describes a novel loop-structured switching network (LSSN) intended for highly parallel processing architectures. With L loops, it can connect up to N = L* log2 L pairs of transmitting and receiving devices using only N/2 two-by-two switching elements; thus, it is very cost-effective in terms of its component count. Its topology resembles that of the indirect binary n-cube network, but a much higher device-to-switch ratio is achieved because all the links between the switches could be used as both transmitting and receiving stations. It has the advantage of incremental extensibility, and-it could avoid store-and-forward deadlocks (SFD) which prevail in other recirculating packet-switched networks. Our simulation studies show that the average throughput rate and delay of LSSN are close to that of other designs despite its relatively low component count.
Index Terms:
recirculating networks, Deadlock avoidance methods, packet switching, parallel processing architectures
F.S. Wong, M.R. Ito, "A Loop-Structured Switching Network," IEEE Transactions on Computers, vol. 33, no. 5, pp. 450-455, May 1984, doi:10.1109/TC.1984.1676462
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