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| F.P. Preparata, W., Jr. Lipski, "Optimal Three-Layer Channel Routing," IEEE Transactions on Computers, vol. 33, no. 5, pp. 427-437, May, 1984. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1984.1676459, author = {F.P. Preparata and W., Jr. Lipski}, title = {Optimal Three-Layer Channel Routing}, journal ={IEEE Transactions on Computers}, volume = {33}, number = {5}, issn = {0018-9340}, year = {1984}, pages = {427-437}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1984.1676459}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Optimal Three-Layer Channel Routing IS - 5 SN - 0018-9340 SP427 EP437 EPD - 427-437 A1 - F.P. Preparata, A1 - W., Jr. Lipski, PY - 1984 KW - VLSI layouts KW - Channel routing KW - multilayer wiring KW - optimal algorithms KW - VLSI design VL - 33 JA - IEEE Transactions on Computers ER - | |||
In this paper we show that any channel routing problem of density d involving only two-terminal nets can always be solved in the knock-knee mode in a channel of width equal to the density d with three conducting layers. An algorithm is described which produces in time O(n log n) (in its simplest implementation) a layout of n nets with the following properties: 1) it has minimal width d; 2) it can be realized with three layers; 3) it has at most 3n vias; 4) any two wires share at most four grid points. Without sacrificing any of the above properties (but possibly obtaining slightly longer wires), the layout algorithm can be modified to run in time ?(n).
Index Terms:
VLSI layouts, Channel routing, multilayer wiring, optimal algorithms, VLSI design
Citation:
F.P. Preparata, W., Jr. Lipski, "Optimal Three-Layer Channel Routing," IEEE Transactions on Computers, vol. 33, no. 5, pp. 427-437, May 1984, doi:10.1109/TC.1984.1676459
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