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Issue No.04 - April (1984 vol.33)
pp: 357-360
C.-S. Yeh , Department of Electrical Engineering, University of Southern California
ABSTRACT
Two systolic architectures are developed for performing the product?sum computation AB + C in the finite field GF(2<sup>m</sup>) of 2<sup>m</sup>elements, where A, B, and C are arbitrary elements of GF(2<sup>m</sup>). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The first m
INDEX TERMS
systolic array, Finite field, logic design, primitive element
CITATION
C.-S. Yeh, I.S. Reed, T.K. Truong, "Systolic Multipliers for Finite Fields GF(2<sup>m</sup>)", IEEE Transactions on Computers, vol.33, no. 4, pp. 357-360, April 1984, doi:10.1109/TC.1984.1676441
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