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Fault-Tolerant 256K Memory Designs
April 1984 (vol. 33 no. 4)
pp. 314-322
R.M. Tanner, Department of Computer and Information Sciences, University of Califomia
A series of designs for a 256K memory are presented which integrate error-correcting coding into the memory organization. Starting from a simple single-error correcting product code, the successive designs explore trade-offs in coding efficiency, access delay, and complexity of communication and computation. In the most powerful design, all the 256K bits are organized so that they form a codeword in a double-error-correcting triple-error-detecting code derived from a projective plane. Because all of the bits are components of this single codeword, the coding efficiency is very high; the required parity check bits increase the storage by only 3 percent, approximately. Single error correction can take place at the time of a read with very little additional delay compared to that of a normal irredundant memory. Multiple error correction can be performed by the memory management system. A variety of failure modes, including failure of a whole column of one of the constituent 64 x 64 subarrays can be tolerated. Writing into the memory is somewhat slower than in a conventional memory, involving a read-write cycle.
Index Terms:
VLSI, Distributed, error-correction, fault-tolerant, memory, parallel, projective plane graph, redundancy
Citation:
R.M. Tanner, "Fault-Tolerant 256K Memory Designs," IEEE Transactions on Computers, vol. 33, no. 4, pp. 314-322, April 1984, doi:10.1109/TC.1984.1676436
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