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Issue No.02 - February (1984 vol.33)
pp: 178-189
null Kuang Yung Liu , Jet Propulsion Laboratory, California Institute of Technology
ABSTRACT
In this paper, the known decoding procedures for Reed-Solomon (RS) codes are modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipelining. The chip architectures of two basic building blocks for VLSI RS decoder systems are then presented. It is shown that a VLSI RS decoder has the potential advantage of achieving a high decoding speed through parallel-pipeline processing.
INDEX TERMS
VLSI, BCH decoders, error-correcting codes, finite field processors, parallel processing, pipeline processing, Reed?Solomon decoders
CITATION
null Kuang Yung Liu, "Architecture for VLSI Design of Reed-Solomon Decoders", IEEE Transactions on Computers, vol.33, no. 2, pp. 178-189, February 1984, doi:10.1109/TC.1984.1676409
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