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February 1984 (vol. 33 no. 2)
pp. 160-177
R.E. Bryant, Department of Computer Science, 256-80, California Institute of Technology
The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper we present a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs. Then we describe an algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, we have achieved a greater degree of generality and accuracy than is found in other logic simulators for MOS.
Index Terms:
VLSI, MOS logic simulation, switch-level model
R.E. Bryant, "A Switch-Level Model and Simulator for MOS Digital Systems," IEEE Transactions on Computers, vol. 33, no. 2, pp. 160-177, Feb. 1984, doi:10.1109/TC.1984.1676408
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