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Bit-Sequential Arithmetic for Parallel Processors
January 1984 (vol. 33 no. 1)
pp. 7-20
Henk J. Sips, Department of Applied Physics, Deift University of Technology, Lorentzweg 1 2628CJ Deift, Holland.
A bit-sequential processing element with O(n) complexity is described, where n is the wordlength of the operands. The operations performed by the element are A * B + C * D, A/B, and ¿A. The operands are fixed point or floating point numbers with variable precision. The concept of semi-on-line algorithms is introduced. A processing element that uses semi-on-line algorithms produces a result ¿ clock cycles after the absorption of the n-bit operands, where ¿ is small compared to n. In the paper the processing element and the algorithms are described. A performance comparison between the bit-sequential processing element and conventional pipelined arithmetic units is given.
Citation:
Henk J. Sips, "Bit-Sequential Arithmetic for Parallel Processors," IEEE Transactions on Computers, vol. 33, no. 1, pp. 7-20, Jan. 1984, doi:10.1109/TC.1984.5009311
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