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VLSI Array Design Under Constraint of Limited I/O Bandwidth
December 1983 (vol. 32 no. 12)
pp. 1160-1170
P.S. Liu, Department of Electrical and Computer Engineering, University of Miami
VLSI computing arrays for matrix multiplication and covariance matrix inversion have applications in many fields. Under the constraint of limited I/O bandwidth of the host system or the computing array, three configurations for the interfacing and controlling of a multiplication array to achieve optimal performance under different adverse situations are examined. The three configurations are multiplexing loading, processor row loading, and processor column group loading. A properly chosen configuration can significantly reduce the computing time of the multiplication array.
Index Terms:
VLSI implementation, Design constraints, image processing, matrix inversion array, multiplication array, performance analysis, reconfigurable VLSI array, signal processing, VLSI architecture
Citation:
P.S. Liu, T.Y. Young, "VLSI Array Design Under Constraint of Limited I/O Bandwidth," IEEE Transactions on Computers, vol. 32, no. 12, pp. 1160-1170, Dec. 1983, doi:10.1109/TC.1983.1676177
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