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Exhaustive Test Pattern Generation with Constant Weight Vectors
December 1983 (vol. 32 no. 12)
pp. 1145-1150
D.T. Tang, IBM Thomas J. Watson Research Center
We develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size. It is shown that such a test set may be formed with vectors of a particular set of weights. Main theorems and examples are established and illustrated in the binary case (for 2-value logic circuits) and then generalized to nonbinary cases (for multivalue logic circuits). Such test sets are simple in structure and become optimal in size in certain cases. It is also shown that such a test set can be effectively implemented via a scan path type shifter.
Index Terms:
VLSI testing, Constant weight codes, exhaustive testing, fault testing, logic testing, multilevel logic, scan path, self-testing, test pattern generation
Citation:
D.T. Tang, L.S. Woo, "Exhaustive Test Pattern Generation with Constant Weight Vectors," IEEE Transactions on Computers, vol. 32, no. 12, pp. 1145-1150, Dec. 1983, doi:10.1109/TC.1983.1676175
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