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Issue No.12 - December (1983 vol.32)
pp: 1137-1144
H. Fujiwara , Department of Electronic Engineering, Osaka University
ABSTRACT
In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.
INDEX TERMS
test generation, Combinational logic circuits, D-algorithm, decision tree, multiple backtrace, PODEM algorithm, sensitization, stuck faults
CITATION
H. Fujiwara, T. Shimono, "On the Acceleration of Test Generation Algorithms", IEEE Transactions on Computers, vol.32, no. 12, pp. 1137-1144, December 1983, doi:10.1109/TC.1983.1676174
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