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December 1983 (vol. 32 no. 12)
pp. 1081-1090
L.N. Bhuyan, Department of Electrical and Computer Engineering, University of Southwestern Louisiana
This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconnection networks depending on how M nd N are factored. The network covers a broad spectrum of interconnections, starting from shared bus to crossbar switches and also includes various multistage interconnection networks (MIN's).
Index Terms:
probability of acceptance, Bandwidth, cost factor, generalized shuffle, m-shuffle, mixed radix number system, multistage interconnection networks, network optimization, permutation and combination
Citation:
L.N. Bhuyan, D.P. Agrawal, "Design and Performance of Generalized Interconnection Networks," IEEE Transactions on Computers, vol. 32, no. 12, pp. 1081-1090, Dec. 1983, doi:10.1109/TC.1983.1676168
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