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Delayed-Staging Hierarchy Optimization
November 1983 (vol. 32 no. 11)
pp. 1029-1037
G.M. Silberman, IBM Thomas J. Watson Research Center
A geometric programming model is developed to optimize delayed-staging (DS) storage hierarchies. These hierarchies have direct paths between the CPU and the k fastest storage levels (k = 1 in a linear hierarchy), allowing for some concurrency in the flow of data through the hierarchy. The criterion for optimization is the minimization of average hierarchy access time subject to budgetary limitations, given the cache access time and the backing-store capacity.
Index Terms:
storage hierarchies, Average access time, delayed-staging, geometric programming, miss ratios
Citation:
G.M. Silberman, "Delayed-Staging Hierarchy Optimization," IEEE Transactions on Computers, vol. 32, no. 11, pp. 1029-1037, Nov. 1983, doi:10.1109/TC.1983.1676153
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