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Strategies for Managing the Register File in RISC
November 1983 (vol. 32 no. 11)
pp. 977-989
Y. Tamir, Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California
The RISC (reduced instruction set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecture is a large register file which is used to minimize the overhead involved in procedure calls and returns. This paper investigates several strategies for managing this register file. The costs of practical strategies are compared with a lower bound on this management overhead, obtained from a theoretical optimal strategy, for several register file sizes.
Index Terms:
VLSI processor, Cache fetch strategies, computer architecture, procedure calls, register file management, RISC
Citation:
Y. Tamir, C.H. Sequin, "Strategies for Managing the Register File in RISC," IEEE Transactions on Computers, vol. 32, no. 11, pp. 977-989, Nov. 1983, doi:10.1109/TC.1983.1676149
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