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Issue No.10 - October (1983 vol.32)
pp: 902-910
A.L. Rosenberg , Department of Computer Science, Duke University
ABSTRACT
This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows.
INDEX TERMS
trees of processors, Arrays of processors, design for testability, dynamic fault tolerance, fault-tolerant design, grids of processors, linear arrays of processors, reconfigurable designs
CITATION
A.L. Rosenberg, "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors", IEEE Transactions on Computers, vol.32, no. 10, pp. 902-910, October 1983, doi:10.1109/TC.1983.1676134
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