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Issue No.09 - September (1983 vol.32)
pp: 878-880
R. Gnanasekaran , Department of Electrical Engineering, Gannon University
ABSTRACT
A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.
INDEX TERMS
two's complement number representation, Add-shift multiplier, bit-sequential multiplier, carry-save addition, on-line multiplication
CITATION
R. Gnanasekaran, "On a Bit-Serial Input and Bit-Serial Output Multiplier", IEEE Transactions on Computers, vol.32, no. 9, pp. 878-880, September 1983, doi:10.1109/TC.1983.1676341
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