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September 1983 (vol. 32 no. 9)
pp. 809-825
T.F. Schwab, Bell Laboratories
In this paper, an algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the neccessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.
Index Terms:
syndrome function, Boolean vector algebra, error correction, fault-tolerant VLSI, fault-masking logic circuits, redundancy, reliability
Citation:
T.F. Schwab, S.S. Yau, "An Algebraic Model of Fault-Masking Logic Circuits," IEEE Transactions on Computers, vol. 32, no. 9, pp. 809-825, Sept. 1983, doi:10.1109/TC.1983.1676330
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