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A Two's Complement Array Multiplier Using True Values of the Operands
August 1983 (vol. 32 no. 8)
pp. 745-747
N. Bandeira, Department of Electrical and Computer Engineering, University of California
A new algorithm for implementing the two's complement multiplication of an m ? n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the Pezaris array and uses less hardware than the Baugh-Wooley implementation.
Index Terms:
Pezaris multiplier, Array multiplier, Baugh-Wooley multiplier, binary multiplication, celluar-subtractor multiplier, parallel multiplier
N. Bandeira, K. Vaccaro, J.A. Howard, "A Two's Complement Array Multiplier Using True Values of the Operands," IEEE Transactions on Computers, vol. 32, no. 8, pp. 745-747, Aug. 1983, doi:10.1109/TC.1983.1676312
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