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Area?Time Optimal VLSI Circuits for Convolution
July 1983 (vol. 32 no. 7)
pp. 684-688
G.M. Baudet, Department of Computer Science, Brown University
A family of VLSI circuits is presented to perform open convolution, i.e., polynomial multiplication. The circuits are all based on a recursive construction and are therefore particularly well adapted to automated design. All the circuits presented are optimal with respect to the area?time2 tradeoff, and, depending on the degree of paralleism or pipeline, they range from a compact but slow convolver to a large but very fast convolver.
Index Terms:
VLSI design, Area-time optimality, convolution
Citation:
G.M. Baudet, F.P. Preparata, J.E. Vuillemin, "Area?Time Optimal VLSI Circuits for Convolution," IEEE Transactions on Computers, vol. 32, no. 7, pp. 684-688, July 1983, doi:10.1109/TC.1983.1676300
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