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Issue No.07 - July (1983 vol.32)
pp: 637-648
D.P. Agrawal , Department of Electrical and Computer Engineering, North Carolina State University
ABSTRACT
This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2n-input/2n-output Multistage Interconnection Networks (MIN's), implemented with 2-input/2-output Switching Elements (SE's) and satisfying a characteristics called the "buddy property." These models show that all such n-stage MIN's are topologically equivalent and hence prove that one MIN can be implemented from integrated circuits designed for another MIN. The proposed techniques also allow identical modeling and comparison of permutation capabilities of n-stage MIN's and other link-controlled networks like augmented data manipulator and SW Banyan Network and hence, allows comparison of their permutation. In the case of any conflict in the MIN, an upper bound for the required number of passes has been obtained.
INDEX TERMS
topological equivalence, Benes network, buddy property, conflict-free permutations, graph modeling, multistage interconnection networks, number of passes, permutability, single-stage network
CITATION
D.P. Agrawal, "Graph Theoretical Analysis and Design of Multistage Interconnection Networks", IEEE Transactions on Computers, vol.32, no. 7, pp. 637-648, July 1983, doi:10.1109/TC.1983.1676295
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