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Issue No.06 - June (1983 vol.32)
pp: 569-581
D. Nath , National Institute of Information Technology
In this paper we describe two interconnection networks for parallel processing, namely the orthogonal trees network and the orthogonal tree cycles (OTN and OTC). Both networks are suitable for VISI implementation and have been analyzed using Thompson's model of VLSI. While the OTN and OTC have time performances similar to fast networks such as the perfect shuffle network (PSN), the cube comnected cycles (CCC), etc., they have substantially better area * time2 performances for a number of matrix and graph problems. For instance, the connected components and a minimal spanning tree of an undirected N-vertex graph can be found in 0(log4 N) time on the OTC with an area * time2 performance of 0(N2 log8 N) and 0(N2 log9 N) respectively. This is asymptoticaly much better than the performances of the CCC, PSN and Mesh. The OTC and OTN can be looked upon as general purpose parallel processors since a number of other problems such as sorting and DFT can be solved on them with an area * time2 performance matching that of other networks. Finally, programming the OTN and OTC is simple and they are also amenable to pipelining a series of problems.
VLSI, Area-time complexity, interconnection networks, matrix multiplication, orthogonal trees networks, parallel algorithms, parallel processing, sorting
S.N. Maheshwari, D. Nath, "Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees", IEEE Transactions on Computers, vol.32, no. 6, pp. 569-581, June 1983, doi:10.1109/TC.1983.1676279
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