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Code Constructions for Error Control in Byte Organized Memory Systems
June 1983 (vol. 32 no. 6)
pp. 535-542
L.A. Dunning, Department of Computer Science, Bowling Green State University
Error correcting codes, such as Hamming codes, have been used successfully to correct errors arising from failures in computer memories. Failure of a chip or card can cause errors which exceed the capabilities of these codes. We construct codes which detect any byte error and correct such errors if they are single random errors. A subclass of the codes developed is shown to have the additional capability of detecting double errors. These codes are intended for use when data are packaged on a byte per chip or a byte per card basis. The codes require fewer check bits than any previously known to the authors except when the byte length or number of bytes is small.
Index Terms:
SEC-BED codes, Byte errors, byte organization, error-correcting codes, error-detecting codes, fault tolerance, linear codes, memories, package failures
Citation:
L.A. Dunning, M.R. Varanasi, "Code Constructions for Error Control in Byte Organized Memory Systems," IEEE Transactions on Computers, vol. 32, no. 6, pp. 535-542, June 1983, doi:10.1109/TC.1983.1676275
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