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A Fully Parallel Mixed-Radix Conversion Algorithm for Residue Number Applications
April 1983 (vol. 32 no. 4)
pp. 398-402
C.H. Huang, Communication Sciences Laboratory, Lockheed Palo Alto Research Laboratory
A new, fully parallel mixed-radix conversion (MRC) algorithm which utilizes the maximum parallelism that exists in the residues (RNS) to mixed-radix (MR) digits conversion to achieve high throughput rate and very short conversion time is presented. The new algorithm has a conversion time of two table look-up cycles for moduli sets consisting of up to 15 moduli. As a comparison, the classical Szabo and Tanaka MRC algorithm has a conversion time of (n - 1) clock cycles for an n-moduli RNS. This algorithm can be implemented by off-the-shelf ECL IC's to achieve a conversion time of 50 ns and a throughput rate of 40 MHz for a 150-bit RNS.
Index Terms:
residue number system, General computing, mixed-radix conversion, parallel and pipelined architecture
Citation:
C.H. Huang, "A Fully Parallel Mixed-Radix Conversion Algorithm for Residue Number Applications," IEEE Transactions on Computers, vol. 32, no. 4, pp. 398-402, April 1983, doi:10.1109/TC.1983.1676242
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