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Issue No.03 - March (1983 vol.32)
pp: 315-319
null Kuang-Wei Chiang , Department of Electrical Engineering and Computer Science, University of Toronto
ABSTRACT
A tree representation of a combinational network is developed. An algorithm is proposed for finding the functional expression realized by the network. The tree representation has storage requirement linear with respect to the number of input-output paths in the network. It is shown that rmding the complementary function and generating network SPOOF can be performed efficiently on the tree structure.
INDEX TERMS
testing, Combinational network model, fault detection, logic circuits
CITATION
null Kuang-Wei Chiang, Z.G. Vranesic, "A Tree Representation of Combinational Networks", IEEE Transactions on Computers, vol.32, no. 3, pp. 315-319, March 1983, doi:10.1109/TC.1983.1676224
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