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Partitioned Matrix Algorithms for VLSI Arithmetic Systems
December 1982 (vol. 31 no. 12)
pp. 1215-1224
null Kai Hwang, School of Electrical Engineering, Purdue University
A new class of partitioned matrix algorithms is developed for possible VLSI implementation of large-scale matrix solvers. Fast matrix solvers are higherly demanded in signal/image processing and in many real-time and scientific applications. Only a few functional types of VLSI arithmetic chips are needed for submatrix computations after partitioning. This partitioned approach is not restricted by problem sizes and thus can be applied to solve arbitrarily large linear systems of equations in an iterative fashion. The following four matrix computations are shown systematically partitionable into submatrix operations, which are feasible for direct VLSI implementation.
Index Terms:
very large scale integration (VLSI), Computer architecture, computer arithmetic, linear system of equations, matrix computations, numerical analysis, parallel processing, real-time applications
Citation:
null Kai Hwang, null Yeng-Heng Cheng, "Partitioned Matrix Algorithms for VLSI Arithmetic Systems," IEEE Transactions on Computers, vol. 31, no. 12, pp. 1215-1224, Dec. 1982, doi:10.1109/TC.1982.1675945
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