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Memory Interference in Synchronous Multiprocessor Systems
November 1982 (vol. 31 no. 11)
pp. 1116-1121
D.W.L. Yen, IBM San Jose Research Laboratory
Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate when request rate is near 1, and M and N are large. Accuracy is established with respect to probabilistic simulation. Additional related models are described.
Index Terms:
performance evaluation, Analytical models, memory bandwidth, memory interference, multiprocessor systems
D.W.L. Yen, J.H. Patel, E.S. Davidson, "Memory Interference in Synchronous Multiprocessor Systems," IEEE Transactions on Computers, vol. 31, no. 11, pp. 1116-1121, Nov. 1982, doi:10.1109/TC.1982.1675928
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