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Minimization of Interprocessor Communication for Parallel Computation
November 1982 (vol. 31 no. 11)
pp. 1067-1075
K.B. Irani, Department of Electrical and Computer Engineering, University of Michigan
This paper is concerned with minimizing the delay due to data communication during the execution of a parallel algorithm on an SIMD computer with a two-way circular unit-shift interconnection network. Algorithms are developed which determine, for a given parallel procedure, the order of computation within that procedure, for every parallel arithmetic expression, the alignment of operands for every binary operation, and the mapping and remapping of data into physical memories so that the communication cost is minimized. The proposed algorithms are applicable to array variables with special types of index functions.
Index Terms:
SIMD computer, Data storage schemes, interconnection networks, interprocessor communication, parallel computation
K.B. Irani, null Kuo-Wei Chen, "Minimization of Interprocessor Communication for Parallel Computation," IEEE Transactions on Computers, vol. 31, no. 11, pp. 1067-1075, Nov. 1982, doi:10.1109/TC.1982.1675923
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