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Systolic Processing and an Implementation for Signal and Image Processing
October 1982 (vol. 31 no. 10)
pp. 1000-1009
A.V. Kulkarni, Advanced Processor Technology Laboratory, ESL, Inc.
Many signal and image processing applications impose a severe demand on the I/O bandwidth and computation power of general-purpose computers. The "systolic" concept offers guidelines in building cost-effective systems that balance I/O with computation. The resulting simplicity and regularity of such systems leads to modular designs suitable for VLSI implementation. We describe here a linear systolic array capable of evaluating a large class of inner-product functions used in signal and image processing. These include matrix multiplication, multidimensional convolutions using fixed or time-varying kernels, as well as various nonlinear functions of vectors. The system organization of a working prototype is also described.
Index Terms:
2-D convolution, Discrete Fourier transform, image processing, inner products, matrix multiplication, 1-D convolution, systolic array, signal processing, systolic processor
Citation:
A.V. Kulkarni, D.W.L. Yen, "Systolic Processing and an Implementation for Signal and Image Processing," IEEE Transactions on Computers, vol. 31, no. 10, pp. 1000-1009, Oct. 1982, doi:10.1109/TC.1982.1675909
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