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A Hardware Hashing Scheme in the Design of a Multiterm String Comparator
September 1982 (vol. 31 no. 9)
pp. 825-834
F.J. Burkowski, Department of Computer Science, University of Waterloo
This paper discusses the hardware design of a term detection unit which may be used in the scanning of text emanating from a serial source such as disk or bubble memory. The main objective of this design is the implementation of a high performance unit which can detect any one of many terms (e.g., 1024 terms) while accepting source text at disk transfer rates. The unit incorporates "off-the-shelf" currently available chips. The design involves a hardware-based hashing scheme that allows incoming text to be compared to selected terms in a RAM which contains all of the strings to be detected. The organization of data in the RAM of the term detector is dependent on a graph-theoretic algorithm which computes maximal matchings on bipartite graphs. The capability of the unit depends on various parameters in the design, and this dependence is demonstrated by means of various tables that report on the results of various simulation studies.
Index Terms:
text scanning, Document retrieval, hardware hashing, term detection, text retrieval systems
Citation:
F.J. Burkowski, "A Hardware Hashing Scheme in the Design of a Multiterm String Comparator," IEEE Transactions on Computers, vol. 31, no. 9, pp. 825-834, Sept. 1982, doi:10.1109/TC.1982.1676098
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