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August 1982 (vol. 31 no. 8)
pp. 791-795
N.R. Strader, Department of Electrical Engineering, Texas A&M University
A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculation of a 2k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on the number of bits in the product. The internal logic for generating the inputs to the carry-save adders is given. This cell directly accepts the bit-serial inputs and generates a bit-serial output. Longer binary operands can be multiplied by simply cascading identical cells without change to existing cells. A given multiplier can process shorter operands in correspondingly shorter times. Applicability of this technique to VLSI implementation of the basic multiply/add operation useful in signal processing algorithms is described.
Index Terms:
VLSI multiplication algorithms, Bit sequential multiplication, carry-save multiplication, computer arithmetic, fast multipliers, real-time signal processors, serial multiplication
Citation:
N.R. Strader, V.T. Rhyne, "A Canonical Bit-Sequential Multiplier," IEEE Transactions on Computers, vol. 31, no. 8, pp. 791-795, Aug. 1982, doi:10.1109/TC.1982.1676085
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